Field of the Invention
Embodiments of the present invention relate generally to the field of memory management and, more specifically, a control mechanism for fine-tuned cache to backing-store synchronization.
Description of the Related Art
One element of a memory subsystem within certain processing units is a Level 2 Cache memory (referred to herein as an “L2 cache”). The L2 cache serves as an intermediate storage area between an external memory and clients that interface with the memory subsystem. In particular, the L2 cache temporarily stores data that the clients are reading from and writing to the external memory. As a result, the data stored in the L2 cache is not always identical to the data stored in the external memory. Specifically, data stored in the L2 cache that is not also stored in the external memory is referred to herein as “dirty data,” which remains in the L2 cache until the data has been “cleaned” by frame buffer logic included in the memory subsystem.
Cleaning dirty data out of the L2 cache is executed according to a variety of well-known techniques. One particular technique involves implementing logic within the memory subsystem (referred to herein as “L2 cache logic”) that detects data writes into the L2 cache and then transmits notifications about the data writes to the frame buffer logic. More specifically, when dirty data is written into a line of the L2 cache, the L2 cache logic immediately transmits a dirty data notification to the frame buffer logic that indicates the line in the L2 cache that now includes dirty data. In turn, the frame buffer logic queues the notification for processing and eventually cleans the L2 cache by copying dirty data from the L2 cache to the external memory.
Notably, the evolution of computing is introducing new manners in which data is written into the L2 cache. Take, for example, a graphics application that is configured to execute a large number of write operations (i.e., updates) to data stored in a line of the L2 cache, where the intermediate form of the data is useless and the final form of the data is all that matters. In this example, the L2 cache logic described above generates and transmits to the frame buffer logic a number of dirty data notifications that corresponds to the number of writes made to the L2 cache line. For example, if the graphics application writes data into a first line of the L2 cache, and rapidly executes seven updates to the data in the first line, then eight dirty data notifications are transmitted from the L2 cache logic to the frame buffer logic. Considering that the final data (i.e., the data after the seventh update) is all that matters—and that one or more of the additional write operations may update the data before the frame buffer logic is able to respond to even the first dirty data notification sent in response to the first write operation—many of these dirty data notifications are superfluous and unneeded for the graphics application to execute properly. Moreover, these dirty data notifications consume energy and bandwidth of the communication channel between the L2 cache logic and the frame buffer logic, which decreases the overall efficiency of the memory subsystem.
As the foregoing illustrates, what is needed in the art is a technique to more effectively manage the transmission of notifications from the L2 cache logic to the frame buffer logic.